1. Field of the Invention
The present invention relates to a D-type flip-flop circuit.
2. Description of Related Art
Presently, while a frequency dividing circuit operable for higher frequency is desired in the technology of a PLL frequency synthesizer, a master-slave type D-type flip-flop circuit composed of bipolar transistors (hereinafter referred to simply as a transistor) is being used.
FIG. 16 shows a structure of such a D-type flip-flop circuit wherein a master circuit 161 comprises a differential circuit 162 for inputting data, a differential circuit 163 for holding data, a current supplying circuit 164 for supplying a current to the differential circuits 162 and 163 and a switching circuit 165 for alternately supplying the current to the differential circuits 162 and 163.
The differential circuit 162 comprises transistors q1 and q2 whose emitters are connected in common, whose bases receive data which are signals inverted from each other and whose collectors are set as outputs. It is noted that the collectors of these transistors q1 and q2 are connected to a source terminal VCC via resistors r1 and r2. While the differential circuit 162 receives input data which are signals inverted from each other via input terminals d1 and d2, it may also be a circuit in which one of the input terminals d1 and d2 is fixed to a reference potential. The differential circuit 163 comprises transistors q3 and q4 whose emitters are connected in common and whose bases and collectors are connected across each other. It is noted that the collectors of the transistors q3 and q4 of the differential circuit 163 are connected to the collectors of the transistors q1 and q2 of the first differential circuit 162, respectively, to receive and hold the outputs from the differential circuit 162. The current supplying circuit 164 comprises a transistor q5 which receives a current value setting signal from a current value setting terminal VCS at its base and whose emitter is connected to a source terminal GND. The switching circuit 165 comprises a pair of transistors q6 and q7 whose respective collectors are connected to emitter connecting points ce1 and ce2 of the respective differential circuits 162 and 163 and whose respective emitters are connected in common to a collector of the transistor q5 of the current supplying circuit 164. The transistors q6 and q7 turn on alternately and supply the currents to the differential circuits 162 and 163, respectively, by receiving clock signals which are inverted from each other at their bases via respective clock terminals cl1 and cl2.
A slave circuit 166 is also constructed in the same manner as the master circuit 161. Bases of transistors q8 and q9 of a differential circuit 167 for inputting data in the slave circuit 166 are connected to the collectors of the transistors q3 and q4 of the differential circuit 163 in the master circuit 161, respectively, to receive the output data held in the differential circuit 163. In the slave circuit 166, collectors of transistors q10 and q11 of a fourth differential circuit 168 for holding data are set as output terminals. A base of a transistor q12 of a current supplying circuit 169 is connected to the current value setting terminal VCS in common with the base of the transistor q5 of the current supplying circuit 164. Therefore, the currents having almost the same value are supplied to the respective differential circuits of the master circuit 161 and the slave circuit 166. A switching circuit 170 comprises transistors q13 and q14 whose respective collectors are connected to emitter connecting points ce3 and ce4 of the respective differential circuits 167 and 168 and whose respective emitters are connected in common to a collector of the transistor q12 of the current supplying circuit 169. The transistors q13 and q14 turn on alternately and supply the currents to the differential circuits 167 and 168, respectively, by receiving the clock signals at their bases via the clock terminals cl2 and cl1.
In the D-type flip-flop circuit in FIG. 16 constructed as described above, the first differential circuit 162 writes input data from the input terminals d1 and d2 in correspondence to "H", which means "high state" hereinafter, of the clock signal of the clock terminal cl1 and in the same time, the differential circuit 168 holds output data of the differential circuit 167. Following to that, in response to "H" of the clock signal of the clock terminal cl2 which is a signal inverted from the clock signal of the clock terminal cell, the differential circuit 163 holds the output data of the differential circuit 162 and at the same time, the differential circuit 167 writes in the output data of the differential circuit 162.
Here, the switching circuits 165 and 170 operate as follows. Timing of ON/OFF of the transistor q6 is simultaneous with that of the transistor q14 and timing of ON/OFF of the transistor q7 is simultaneous with that of the transistor q13. When the transistors q6 and q14 are ON, the transistors q7 and q13 are OFF and vice versa. They are turned ON/OFF simultaneously.
It is noted with regard to the expression of ON/OFF used here that although it is unable to clearly distinguish ON/OFF when frequency increases, it is expressed as "the transistor q6 is ON and the transistor q7 is OFF" in a state that "the transistor q6 turns ON strongly as compared to the transistor q7" even when the transistors q6 and q7 turn ON in the same time for example. The same can be said also in the embodiments described later.
However, the D-type flip-flop circuit shown in FIG. 16 has had a trouble in its operation in high frequency because it has not been able to compensate a propagation delay time due to its structure.
That is, in rewriting old data, which have been held in the differential circuit 163 while transistor q7 has been ON, with new (inverted) input data in response to the transistor q6 turning ON for example, the differential circuit 163 continues to hold the old data for a while even when the transistor q7 turns OFF and the transistor q6 turns ON in the same time because of the propagation time. Therefore, the new input data takes an extra load for inverting the old data. Although it is possible to write the data in a shorter time if it is written in a state in which there is no old data because it is not necessary to invert the data and it requires only a load for writing the data. Actually it takes a time to write the data because of the extra load and the writing operation cannot follow the clock signal as operating frequency increases.